Programming an array of resistance random access memory cells using unipolar pulses

ABSTRACT

Subject matter disclosed herein relates to a memory device, and more particularly to programming a non-volatile memory device.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/007,544, filed Jan. 14, 2011, entitled PROGRAMMING AN ARRAY OFRESISTANCE RANDOM ACCESS MEMORY CELLS USING UNIPOLAR PULSES, which ishereby incorporated by reference in its entirety and made part of thisspecification.

BACKGROUND

1. Field

Subject matter disclosed herein relates to a memory device, and moreparticularly to programming a non-volatile memory device.

2. Information

A feature of non-volatile memory devices is that loss of data stored intheir memory cells need not occur if an external power supply isremoved. Thus, such non-volatile memory devices are widely employed in avariety of electronics, including computing systems, mobilecommunication systems, memory cards, and the like.

A resistance random access memory (RRAM) device comprises a type ofnon-volatile memory that uses a variable resistive material layer as adata storage material layer. Such a variable resistive material layermay exhibit reversible resistance variance in accordance with a polarityand/or amplitude of an applied electric pulse, for example.

BRIEF DESCRIPTION OF THE FIGURES

Non-limiting and non-exhaustive embodiments will be described withreference to the following figures, wherein like reference numeralsrefer to like parts throughout the various figures unless otherwisespecified.

FIG. 1 is a plot of current-voltage characteristics of a memory cell,according to an embodiment.

FIG. 2 is a plot of current-voltage characteristics of a memory cell,according to another embodiment.

FIG. 3 is a schematic diagram of a circuit to program a memory cell,according to an embodiment.

FIG. 4 is a schematic diagram of a circuit to program a memory cell,according to another embodiment.

FIG. 5 is a circuit diagram illustrating intrinsic resistance associatedwith a memory cell, according to an embodiment.

FIG. 6 is a schematic diagram of a circuit to program a memory cellincluding intrinsic resistance, according to an embodiment.

FIG. 7 is a schematic diagram of a circuit to program a memory cellincluding intrinsic resistance, according to another embodiment.

FIG. 8 is a plot of characteristics of an electric pulse to program amemory cell, according to an embodiment.

FIG. 9 is a flow diagram of a process to program a memory cell,according to an embodiment.

FIG. 10 is a schematic diagram illustrating an exemplary embodiment of acomputing system.

DETAILED DESCRIPTION

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of claimed subject matter. Thus, theappearances of the phrase “in one embodiment” or “an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in one or moreembodiments.

Resistance random access memory (RRAM) comprises non-volatile memorythat may be applied in electronic devices that would otherwise usefloating gate memory, such as Flash for example. A problem that mayarise with RRAM, however, relates to a set-to-reset state transition ofa unipolar RRAM cell integrated into a memory array. In particular,current-voltage characteristics of a single RRAM cell may be differentfrom those of a RRAM cell that is incorporated in an array of RRAMcells. Programming errors may occur if such different current-voltagecharacteristics are not accounted for while programming an array of RRAMcells. Embodiments described herein include techniques or electronicarchitecture to program RRAM cells in an array from a set state to areset state.

Differences between current-voltage characteristics of a single RRAMcell and current-voltage characteristics of RRAM cells in an array, asmentioned above, may result from circuit elements that may be present inthe array that are not present for the single RRAM cell. For example, anarray of RRAM cells may include wordlines, bitlines, switching diodes,and so on, whereas a single RRAM cell need not include such elements. Aswill be explained in further detail below, wordlines, bitlines, and/orselectors (e.g., diodes, bipolar transistors, MOSFET's, and so on) mayinclude an intrinsic resistance that may affect current-voltagecharacteristics of RRAM cells. In an implementation, intrinsicresistance of bitlines and/or selectors may affect RRAM cells of anarray more so than intrinsic resistance of wordlines because particularprogramming signals are provided to the RRAM cells via bitlines and/orselectors instead of wordlines, for example.

In an embodiment, memory cells of a non-volatile memory device such as aRRAM device may be programmed to be in either a set state, representinglogic “1”, or a reset state, representing logic “0”. A set state of aRRAM cell may comprise a low-resistance state while a reset state maycomprise a high-resistance state. Details of such states will bedescribed below. In an implementation, RRAM cells in an array may beprogrammed from one state to the other state (e.g., reset state to setstate or vise versa) by applying an electric pulse across electrodeterminals of the RRAM cells via bitlines and/or wordlines in the array.As mentioned above, programming a RRAM cell integrated into a memoryarray from a set state to a reset state may present complications,discussed below. (Programming such a RRAM cell from a reset state to aset state need not present complications, however.)

Accordingly, to overcome programming complications, in an embodiment, amethod of programming a RRAM cell from a set state to a reset state mayinclude initiating such a state transition by applying a first portionof an electric pulse to a bitline to deliver enough programming currentfor the state transition (of the order of milliamps, for example). Soonafter switching to a high resistive state, the memory cell may be drivento such an unstable state, which is explained in detail below, for arelatively short time before physical damage to the memory cell orspurious transition to the previous state may occur. Thus, a secondportion of the electric pulse may be applied to the memory cell duringthe resulting state transition to relatively quickly decrease thevoltage of the electric pulse across the cell so as to return the memorycell to a stable state. Such a method of programming a RRAM cell may beperformed by a memory controller, for example. Reasons why such a methodof programming a RRAM cell includes momentarily driving the RRAM cellinto an unstable state are explained in detail below in reference tocurrent-voltage characteristics of the RRAM cell integrated in arelatively dense array. In one implementation, a second portion of anelectric pulse used to return the RRAM cell to a stable state from ahigh-voltage unstable state may comprise a decaying resistor-capacitor(RC) voltage.

FIG. 1 is a plot of current-voltage characteristics 100 of a RRAM cell,according to an embodiment. For example, such a RRAM cell may comprise anickel-oxide (NiO) active material. Such a RRAM cell may exist in a setstate on set-state curve 120 or a reset state on reset-state curve 110,for example. If the RRAM cell is in the set state then current andvoltage of the RRAM cell (e.g., current through the RRAM cell andvoltage across the RRAM cell) may be described by set-state curve 120.For example, the RRAM cell may be in a set state at point 140 on theset-state curve 120. In this case, the RRAM cell may conduct a currentof about 2.0 milliamps with a voltage of about 0.5 volts. A set-state ofa RRAM cell is considered to be a low-resistance state. On the otherhand, if the RRAM cell is in the reset state then current and voltage ofthe RRAM cell may be described by reset-state curve 110. For example,the RRAM cell may be in a reset state at point 145 on the reset-statecurve 110. In this case, the RRAM cell may conduct a current of about0.3 milliamps with a voltage of about 1.25 volts. A reset-state of aRRAM cell is considered to be a high-resistance state.

Transitions from one state to another may be performed by applying anelectric pulse across electrodes of the RRAM cell. Depending on thedesired transition, such an electric pulse may comprise a voltage pulseor a current pulse. For example, a voltage pulse applied to the RRAMcell may initiate a transition from the set state to the reset state viatransition line 125, whereas a current pulse may initiate a transitionfrom the reset state to the set state via transition line 115. Toillustrate by example, if the RRAM cell is in a set state at point 140,then applying a voltage pulse to the RRAM cell may drive the RRAM cellfrom point 140 to set terminus 128. As the voltage of the voltage pulsecontinues to increase beyond set terminus 128, the RRAM cell maytransition via transition line 125 to a reset state on reset-state curve110. Depending, at least in part, on the magnitude of the voltage pulse,the RRAM cell may then be in a reset state at point 145, for example.

In another example, if the RRAM cell is in a reset state at point 145,then applying a current pulse to the RRAM cell may drive the RRAM cellfrom point 145 to reset terminus 118. As the current of the currentpulse continues to increase beyond reset terminus 118, the RRAM cell maytransition via transition line 115 to a set state on set-state curve120. Depending, at least in part, on the magnitude of the current pulse,the RRAM cell may then be in a set state at point 140, for example. Ofcourse, such details of current-voltage characteristics of a RRAM cellare merely examples, and claimed subject matter is not so limited.

FIG. 3 is a schematic diagram of a circuit 300 to program a RRAM cell,according to an embodiment. In particular, circuit 300 may generate acurrent pulse to program RRAM cell 310 from a reset state to a set stateusing a current source 320. A memory controller, for example, mayinitiate such a transition by closing switch S to connect current source320 to RRAM cell 310.

FIG. 4 is a schematic diagram of a circuit 400 to program a RRAM cell,according to an embodiment. In particular, circuit 400 may generate avoltage pulse to program RRAM cell 310 from a set state to a reset stateusing a voltage source 420. A memory controller, for example, mayinitiate such a transition by closing switch S to connect voltage source420 to RRAM cell 310.

As discussed above, the RRAM cell described in FIG. 3 may exist in a setstate on set-state curve 120 or a reset state on reset-state curve 110,for example. Such states may be considered stable states. On the otherhand, if the RRAM cell is driven to a voltage and/or current that isbeyond a range of both the set-state curve 120 and the reset-state curve110, then the RRAM cell may be considered to be in an unstable state.For example, the RRAM cell being driven to a voltage greater than thatof reset terminus 118 (e.g., a voltage greater than about 1.5 volts) maybe considered to be in a high-voltage unstable state, as shown in aright portion of FIG. 1. For another example, the RRAM cell being drivento a current greater than that of set terminus 128 (e.g., a currentgreater than about 2.5 milliamps) may be considered to be in ahigh-current unstable state, as shown in a top portion of FIG. 1. A RRAMcell existing in such unstable states may not reliably maintain storedinformation. In addition, a RRAM cell existing in such unstable statesfor a period of time may succumb to physical damage.

As explained above, differences between current-voltage characteristicsof a single RRAM cell and current-voltage characteristics of RRAM cellsin an array may result from circuit elements that may be present in thearray that are not present for the single RRAM cell. For example, anarray of RRAM cells may include bitlines, wordlines, selectors, and soon, whereas a single RRAM cell need not include such elements. Bitlines,wordlines, and/or selectors may include an intrinsic resistance that mayaffect current-voltage characteristics of RRAM cells in the array,particularly in the set state, wherein relatively large program currentsmay be involved.

FIG. 5 is a schematic diagram of a circuit 500 illustrating inherentresistance associated with a RRAM cell incorporated in an array,according to an embodiment. Intrinsic bitline resistance 520 andintrinsic diode resistance 530 may be in series with RRAM cell 510. Forexample, such intrinsic resistances may be in the order of kilo-ohms fora 45.0 nm technology node with copper metallization, though claimedsubject matter is not so limited.

FIG. 2 is a plot of current-voltage characteristics 200 of a RRAM cellthat may be incorporated in an array of RRAM cells, according to anembodiment. For example, such a RRAM cell may be similar the RRAM cellhaving current-voltage characteristics 100 in FIG. 1, except fordifferences that may arise as a result of the RRAM cell beingincorporated in an array. Accordingly, set-state curve 220 may bemodified as indicated by arrows 233. A modified set-state curve 230 mayresult. In addition, modified set-state curve 230 may include a modifiedset terminus 235, which may be located in a high-voltage unstableportion of current-voltage characteristics 200 for the RRAM cell. Such asituation will be described further below. Other features ofcurrent-voltage characteristics 200 may be similar to that shown inFIG. 1. For example, a RRAM cell may exist in a set state on set-statecurve 230 or a reset state on reset-state curve 210. If the RRAM cell isin the set state then current and voltage of the RRAM cell may bedescribed by set-state curve 230. For example, the RRAM cell may be in aset state at point 240 on the set-state curve 230. In this case, theRRAM cell may conduct a current of about 1.5 milliamps with a voltage ofabout 0.8 volts. Such current may be relatively less than the case shownin FIG. 1 because intrinsic resistances of a memory cell array are takeninto account with modified set-state curve 230 in FIG. 2. If the RRAMcell is in the reset state then current and voltage of the RRAM cell maybe described by reset-state curve 210. For example, the RRAM cell may bein a reset state at point 245 on the reset-state curve 210. In thiscase, the RRAM cell may conduct a current of about 0.3 milliamps with avoltage of about 1.25 volts.

As in the case shown in FIG. 1, transitions from one state to anothermay be performed by applying an electric pulse across electrodes of theRRAM cell. Depending on the desired transition, such an electric pulsemay comprise a voltage pulse or a current pulse. For example, a voltagepulse applied to the RRAM cell may initiate a transition from the setstate to the reset state via transition line 225, whereas a currentpulse may initiate a transition from the reset state to the set statevia transition line 215. In the case for a transition from the set stateto the reset state, however, modified set-state curve 230 may presentfeatures not present if the set-state curve 220 were not modified (e.g.,as in the case for FIG. 1). To illustrate by example, if the RRAM cellis in a set state at point 240, then applying a voltage pulse to theRRAM cell may drive the RRAM cell from point 240 to modified setterminus 235. As mentioned above, modified set terminus 235 may belocated in an unstable region of the RRAM cell. Thus, to continue atransition from the set state to the reset state, and to preventphysical damage to the RRAM cell, the magnitude of the applied voltagepulse may be decreased so that the RRAM cell is driven from modified setterminus 235 to set terminus 228, where the RRAM cell may transition viatransition line 225 to a reset state on reset-state curve 210.Depending, at least in part, on the magnitude of the voltage pulse, theRRAM cell may then be in a reset state at point 245, for example. Thus,in summary, a transition from the set state to the reset state may occurvia a transition path through an unstable state of a RRAM cell.

If the RRAM cell is in a reset state at point 245, then applying acurrent pulse to the RRAM cell may drive the RRAM cell from point 245 toreset terminus 218. As the current of the current pulse continues toincrease beyond reset terminus 218, the RRAM cell may transition viatransition line 215 to a set state on set-state curve 220. Depending, atleast in part, on the magnitude of the current pulse, the RRAM cell maythen be in a set state at point 240, for example. Thus, a process ofperforming a transition from a reset state to a set state of a RRAM cellin an array, as just described, may not be substantially different fromthat of an isolated RRAM cell. On the other hand, a process ofperforming a transition from a set state to a reset state of a RRAM cellin an array may be substantially different from that of an isolated RRAMcell. Accordingly, details of techniques for performing such atransition from a set state to a reset state are described below. Ofcourse, such details of current-voltage characteristics of a RRAM cellincorporated in an array are merely examples, and claimed subject matteris not so limited.

FIG. 6 is a schematic diagram of a drive circuit 600 to program a RRAMcell including intrinsic resistance of array elements, according to anembodiment. For example, RRAM cell 510 may be connected in series withintrinsic bitline (and/or wordline) resistance 520 and intrinsic dioderesistance 530, also shown in FIG. 5. As described above, programmingRRAM cell 510 to transition from a set state to a reset state mayinclude at least momentarily driving RRAM cell 510 into a high-voltageunstable state after the state transition. Such may be the case, forexample, due to a parasitic voltage drop on a programming path that maybe localized across the cell soon after the state transition. In detail,such a transition from a set state to a reset state may be performed byapplying a first portion of an electric pulse to deliver requiredprogramming current to the RRAM cell 510 to overcome parasitic paths,and then applying a second portion of the electric pulse during thetransition to decrease the voltage of the electric pulse to lead theRRAM cell to a stable state. Thus, drive circuit 600 may generate suchan electric pulse that is applied to RRAM cell 510 if switch S isclosed. Characteristics (e.g., the shape) of such an electric pulse maybe tailored to particular features of RRAM cell 510. For example, afirst portion of an electric pulse to deliver required programmingcurrent may have a particular time span, magnitude, and so on. Asanother example, a second portion of the electric pulse to drive RRAMcell 510 into a stable state may have a particular time span, magnitude,decay rate, and so on. Accordingly, a variable current source 670, inconjunction with operational amplifier 660 and shunt resistor 650 may beselected to generate an electric pulse having first and second portionsthat are favorable to perform a state transition of RRAM cell 510without damaging RRAM cell 510. In one implementation, drive circuit 600may perform a real-time verify process using a closed loop feedback to aprogram generator (not shown). A programming pulse may stop in responseto a drop of voltage across shunt resistor 650 that indicates areduction of current across RRAM cell 510 just after switching to a highresistive state. A trigger signal to stop the program generator on aprogramming path may comprise the rising edge of a voltage signal at theoutput of operational amplifier 660, for example. Of course, suchdetails of a drive circuit are merely examples, and claimed subjectmatter is not so limited.

FIG. 7 is a schematic diagram of a drive circuit 700 to program a memorycell including intrinsic resistance, according to another embodiment.Compared with drive circuit 600, drive circuit 700 may be relativelysimple and fast. Drive circuit 700 may also be able to deliversufficient energy/current in a relatively short time, thus avoidingspurious programming of intermediate unstable states of RRAM cell 510while transition from a set state to a reset state. For example, drivecircuit 700 may generate an electric pulse based, at least in part, oncapacitance discharge. Also, drive circuit 700 may generate an electricpulse having a relatively fast response in terms of reducing voltagethrough a RRAM cell shortly after the set to reset transition. Forexample, such a fast response may be desirable for RRAM programmingspeeds of the order of several nanoseconds.

Drive circuit 700 may comprise a capacitor 760 and a parallel variableresistor 750. A first switch S1 may connect drive circuit 700 to RRAM510 and a second switch S2 may connect capacitor 760 to parallelvariable resistor 750. In an implementation, a value of capacitance ofcapacitor 760 may be selected based, at least in part, on a physicaltransition model of RRAM 510. For example, a lower bound for a value ofcapacitance may depend, at least in part, on total energy requiredduring a process of transitioning from a set state to a reset state.Such a lower bound value may be of the order of tens of nano-Farads for90 nm RRAM cell scales). Parallel variable resistor 750 may be adjustedto determine a compromise between required energy and a voltage RC toprovide a relatively fast discharge across capacitor 760 subsequent to aset to reset transition. In other words, a value of resistance may behigh enough to ensure a required peak current through RRAM cell 510while being low enough to ensure a relatively fast capacitance dischargesoon after cell transition from low resistive (set) state to highresistive (reset) state. Again, such details of a drive circuit aremerely examples, and claimed subject matter is not so limited.

FIG. 8 is a plot of characteristics of an electric pulse 800 to programa memory cell, according to an embodiment. Such an electric pulse may begenerated by circuit 700, for example, to perform a transition from aset state to a reset state of a RRAM cell, as described above. Such aRRAM cell may be incorporated in an array of a memory device, forexample. Electric pulse 800 may comprise a first portion 820 to beapplied to a RRAM cell to initiate a transition from a set state to areset state of the RRAM cell. Such a first portion may drive the RRAMcell into a high-voltage unstable state, as discussed above. Firstportion 820 may include a peak magnitude 810 of electric pulse 800. Asan example, first portion 820 may be applied to RRAM cell 510 (FIG. 7)upon closing first and second switches 51 and S2 (e.g., first switch 51may be closed before second switch S2 to provide electric pulse 800). Inan implementation, point A of electric pulse 800 may correspond to RRAMcell 500 being driven to modified set terminus 235 in a high-voltageunstable state, shown in FIG. 2, for example. For example, referring toFIG. 2, first portion 820 of electric pulse 800 may correspond todriving an RRAM cell from set point 240 to modified set terminus 235. Atsuch a point, it may be desirable to relatively rapidly reduce voltageof electric pulse 800 so as to avoid physical damage to the RRAM celland/or to avoid prolonged time spent in a high-voltage unstable state,which may lead to unpredictable behavior of the RRAM cell (e.g.,including failure to reliably write a bit of information to the RRAMcell). Thus, a second portion 830 of electric pulse 800 may be appliedduring the state transition to decrease a voltage of electric pulse 800so as to return the RRAM cell to a stable state. In an implementation,second portion 830 may comprise an RC decay portion of electric pulse800. Particular values for magnitude, duration, and/or slope for variousportions of electric pulse 800 may be selected for particular RRAMcells. Such particular values may be determined by any of a number oftechniques, including trial and error, for example. Of course, suchdetails of magnitude, duration, and slope of an electric pulse aremerely examples, and claimed subject matter is not so limited.

FIG. 9 is a flow diagram of a process 900 to program a RRAM cell from aset state to a reset state, according to an embodiment. As explainedabove, such a RRAM cell may be incorporated in a memory array. At block910, a memory controller may receive a write command from a processorand/or host entity, for example, to reset the RRAM cell. Accordingly,the memory controller may perform a process of transitioning the RRAMcell from a set state to a reset state. At block 920, the memorycontroller may use circuit 700, for example, to drive the RRAM cell intoa high-voltage unstable state to initiate a transition from a set stateto a reset state. For example, the RRAM cell may be driven into ahigh-voltage unstable state by applying a first portion of an electricpulse, such as that shown in FIG. 8. At block 930, a second portion ofan electric pulse may be applied to the RRAM cell upon or during thetransition from the set state to the reset state. Such a second portionmay relatively rapidly decrease the voltage of the electric pulse so asto return the RRAM cell to a stable state. At block 940, in a particularimplementation, a program-verify process may be performed by the memorycontroller to verify that the RRAM cell was properly programmed to areset state. Thus, the RRAM cell may be read by measuring resistance ofthe RRAM cells. In another particular implementation, a capacitor may becharged to different voltages after each such verify event. As mentionedabove, a reset state of a RRAM cell may comprise a high-resistancestate, so that the RRAM cell in a reset state would be expected to havea relatively high resistance. Of course, such details of process 900 aremerely examples, and claimed subject matter is not so limited.

FIG. 10 is a schematic diagram illustrating an exemplary embodiment of acomputing system 1000 including a memory device 1010, which may compriseRRAM, for example. Such a computing device may comprise one or moreprocessors, for example, to execute an application and/or other code. Acomputing device 1004 may be representative of any device, appliance, ormachine that may be configurable to manage memory device 1010. Memorydevice 1010 may include a memory controller 1015 and a memory 1022. Byway of example but not limitation, computing device 1004 may include:one or more computing devices and/or platforms, such as, e.g., a desktopcomputer, a laptop computer, a workstation, a server device, or thelike; one or more personal computing or communication devices orappliances, such as, e.g., a personal digital assistant, mobilecommunication device, or the like; a computing system and/or associatedservice provider capability, such as, e.g., a database or data storageservice provider/system; and/or any combination thereof.

It is recognized that all or part of the various devices shown in system1000, and the processes and methods as further described herein, may beimplemented using or otherwise including hardware, firmware, software,or any combination thereof. Thus, by way of example but not limitation,computing device 1004 may include at least one processing unit 1020 thatis operatively coupled to memory 1022 through a bus 1040 and a host ormemory controller 1015. Processing unit 1020 is representative of one ormore circuits configurable to perform at least a portion of a datacomputing procedure or process. By way of example but not limitation,processing unit 1020 may include one or more processors, controllers,microprocessors, microcontrollers, application specific integratedcircuits, digital signal processors, programmable logic devices, fieldprogrammable gate arrays, and the like, or any combination thereof.Processing unit 1020 may include an operating system configured tocommunicate with memory controller 1015. Such an operating system may,for example, generate commands to be sent to memory controller 1015 overbus 1040.

Memory controller 1015 may perform commands such as read and/or writecommands initiated by processing unit 1020. In response to a writecommand, for example, memory controller 1015 may initiate a transitionfrom a set state to a reset state of a memory cell of memory device 1010by applying a first portion of an electric pulse to drive the memorycell into a high-voltage unstable state. Subsequently, memory controller1015 may apply a second portion of the electric pulse during thetransition to decrease a voltage of the electric pulse so as to returnthe memory cell to a stable state.

Memory 1022 is representative of any data storage mechanism. Memory 1022may include, for example, a primary memory 1024 and/or a secondarymemory 1026. Memory 1022 may comprise PCM, for example. Primary memory1024 may include, for example, a random access memory, read only memory,etc. While illustrated in this example as being separate from processingunit 1020, it should be understood that all or part of primary memory1024 may be provided within or otherwise co-located/coupled withprocessing unit 1020.

Secondary memory 1026 may include, for example, the same or similar typeof memory as primary memory and/or one or more data storage devices orsystems, such as, for example, a disk drive, an optical disc drive, atape drive, a solid state memory drive, etc. In certain implementations,secondary memory 1026 may be operatively receptive of, or otherwiseconfigurable to couple to, a computer-readable medium 1028.Computer-readable medium 1028 may include, for example, any medium thatcan carry and/or make accessible data, code, and/or instructions for oneor more of the devices in system 1000.

Computing device 1004 may include, for example, an input/output 1032.Input/output 1032 is representative of one or more devices or featuresthat may be configurable to accept or otherwise introduce human and/ormachine inputs, and/or one or more devices or features that may beconfigurable to deliver or otherwise provide for human and/or machineoutputs. By way of example but not limitation, input/output device 1032may include an operatively configured display, speaker, keyboard, mouse,trackball, touch screen, data port, etc.

While there has been illustrated and described what are presentlyconsidered to be example embodiments, it will be understood by thoseskilled in the art that various other modifications may be made, andequivalents may be substituted, without departing from claimed subjectmatter. Additionally, many modifications may be made to adapt aparticular situation to the teachings of claimed subject matter withoutdeparting from the central concept described herein. Therefore, it isintended that claimed subject matter not be limited to the particularembodiments disclosed, but that such claimed subject matter may alsoinclude all embodiments falling within the scope of the appended claims,and equivalents thereof.

What is claimed is:
 1. A method of programming information to anon-volatile memory cell, comprising: providing a write command forprogramming the information to the non-volatile memory cell; driving thenon-volatile memory cell to an unstable state in response to the writecommand by applying to the non-volatile memory cell a first portion ofan electrical programming signal; and returning the non-volatile memorycell from the unstable state to a desired stable state by applying tothe non-volatile memory cell a second portion of the electricalprogramming signal, wherein a plot of magnitude over time of the secondportion of the electrical programming signal has a shape different fromthat of the first portion of the electrical programming signal.
 2. Themethod of claim 1, wherein driving the non-volatile memory cell to theunstable state comprises applying to the non-volatile memory cell thefirst portion of the electrical programming signal at a sufficientlyhigh voltage to drive the non-volatile memory cell to a high voltageunstable state.
 3. The method of claim 2, wherein the electricalprogramming signal comprises a varying voltage, wherein a magnitude ofthe voltage has a peak magnitude in the first portion, the peakmagnitude sufficient to drive the non-volatile memory cell to thehigh-voltage unstable state.
 4. The method of claim 1, wherein thenon-volatile memory cell comprises a resistance random access memory(RRAM) cell, and the write command comprises a command to transition theresistance random access memory cell between a set state and a resetstate.
 5. The method of claim 4, wherein the electrical programmingsignal comprises a voltage signal for transitioning the non-volatilememory cell from the set state to the reset state.
 6. The method ofclaim 5, wherein the voltage signal applied to the non-volatile memorycell in the unstable state comprises a voltage greater than a thresholdswitching voltage of the non-volatile memory cell in the reset state. 7.The method of claim 1, wherein the electrical programming signalcomprises a decreasing electrical programming signal during the secondportion.
 8. The method of claim 7, wherein the decreasing electricalprogramming signal comprises a decaying resistor-capacitor (RC) voltage.9. The method of claim 1, further comprising verifying a properprogramming of the non-volatile memory cell subsequent to returning thenon-volatile memory cell to the desired stable state.
 10. The method ofclaim 1, wherein the non-volatile memory cell is returned to the desiredstable state during applying the second portion of the electricalprogramming signal.
 11. A memory device comprising: a memory arraycomprising a non-volatile memory cell; and a memory controllerconfigured to program information to the non-volatile memory cell of thememory array by: receiving a write command to program the information tothe non-volatile memory cell; driving the non-volatile memory cell to anunstable state in response to the write command by applying to thenon-volatile memory cell a first portion of an electrical programmingsignal; and returning the non-volatile memory cell from the unstablestate to a desired stable state by applying to the non-volatile memorycell a second portion of the electrical programming signal, wherein aplot of magnitude over time of the second portion of the electricalprogramming signal has a shape different from that of the first portionof the electrical programming signal.
 12. The memory device of claim 11,wherein the memory array comprises a resistance random access memory(RRAM), and the write command comprises a command to transition thenon-volatile memory cell between a set state and a reset state.
 13. Thememory device of claim 11, wherein driving the non-volatile memory cellto the unstable state comprises applying to the non-volatile memory cellthe first portion of the electrical programming signal at a sufficientlyhigh voltage to drive the non-volatile memory cell to a high voltageunstable state.
 14. The memory device of claim 13, wherein theelectrical programming signal comprises a varying voltage, wherein amagnitude of the voltage has a peak magnitude in the first portion, thepeak magnitude sufficient to drive the non-volatile memory cell to thehigh voltage unstable state.
 15. The memory device of claim 11, whereinthe electrical programming signal comprises a decreasing electricalprogramming signal during the second portion.
 16. The memory device ofclaim 15, wherein the decreasing electrical programming signal comprisesa decaying resistor-capacitor (RC) voltage.
 17. The memory device ofclaim 11, wherein the memory controller comprises a drive circuit havingat least a variable current source, an operational amplifier and a shuntresistor for driving the non-volatile memory cell to an unstable state.18. The memory device of claim 11, wherein the memory controllercomprises a drive circuit having a capacitor and a parallel variableresistor for driving the non-volatile memory cell to an unstable state.19. A system, comprising a memory array comprising a non-volatile memorycell; a processor configured to initiate a write command to programinformation to the non-volatile memory cell of the memory array; and amemory controller configured to program the information to thenon-volatile memory cell by: receiving the write command to program theinformation to the non-volatile memory cell; driving the non-volatilememory cell to an unstable state in response to the write command byapplying to the non-volatile memory cell a first portion of anelectrical programming signal; and returning the non-volatile memorycell from the unstable state to a desired stable state by applying tothe non-volatile memory cell a second portion of the electricalprogramming signal, wherein a plot of magnitude over time of the secondportion of the electrical programming signal has a shape different fromthat of the first portion of the electrical programming signal.
 20. Thesystem of claim 19, wherein driving the non-volatile memory cell to theunstable state comprises applying to the non-volatile memory cell thefirst portion of the electrical programming signal at a sufficientlyhigh voltage to drive the non-volatile memory cell to a high voltageunstable state.
 21. The system of claim 19, wherein the second portionof the electrical programming signal comprises a decayingresistor-capacitor (RC) voltage.